1. Field of the Invention
The present invention relates to a method of forming the gate of an integrated circuit device. More particularly, the present invention relates to a method of forming a T-shaped gate.
2. Description of the Related Art
As the level of integration of integrated circuit rises, dimensions of each semiconductor device are reduced and the adverse effects of having a narrow line width are more prominent.
To counteract the rapid increase in sheet resistance due to a narrow line width, a metal silicide layer is formed over the source, drain and gate terminals of a transistor. Hence, electrical conductivity between a transistor terminal and a conductive line is increased.
Conventionally, the metal silicide layer over transistor terminals is formed by a self-aligned silicide (Salicide) process. After a transistor consisting of a polysilicon gate, a gate oxide layer, a source terminal, a drain terminal and spacers is formed, a metallic layer is formed over the transistor. A thermal operation is conducted so that metallic atoms in the metallic layer can react with silicon atoms on the surface of the polysilicon gate, the source terminal and the drain terminal to form a metal silicide layer. finally, the unreacted metal is removed.
Another method of lowering sheet resistance at the gate besides forming a silicide layer over the gate is to form a T-shaped gate terminal. However, a selective silicon growth process is the conventional method of forming a T-shaped gate terminal. Selective silicon growth is an expensive process and has a small processing window. Therefore, cost of production is high and throughput is low, which means it is not suitable for volume production in a manufacturing facility.